Wikipedia
OpenSPARC
OpenSPARC is an open-source hardware project started in December 2005. The initial contribution to the project was Sun Microsystems' register-transfer level (RTL) Verilog code for a full 64-bit, 32- thread microprocessor, the UltraSPARC T1 processor. On March 21, 2006, Sun released the source code to the T1 IP core under the GNU General Public License. The full OpenSPARC T1 system consists of 8 cores, each one capable to execute 4 threads concurrently, for a total of 32 threads. Each core executes instruction in order and its logic is split among 6 pipeline stages.
On December 11, 2007, Sun also made the UltraSPARC T2 processor's RTL available via the OpenSPARC project. OpenSPARC T2 is 8 cores, 16 pipelines with 64 threads.