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The DLX (pronounced "Deluxe") is a RISC processor architecture designed by John L. Hennessy and David A. Patterson, the principal designers of the Stanford MIPS and the Berkeley RISC designs (respectively), the two benchmark examples of RISC design (named after the Berkeley design).

The DLX is essentially a cleaned up (and modernized) simplified MIPS CPU. The DLX has a simple 32-bit load/store architecture, somewhat unlike the modern MIPS CPU. As the DLX was intended primarily for teaching purposes, the DLX design is widely used in university-level computer architecture courses.

There are two known implementations: ASPIDA and VAMP. ASPIDA project resulted in a core with many nice features: open source, supports Wishbone, asynchronous design, supports multiple ISA's, ASIC proven. VAMP is a DLX-variant that was mathematically verified as part of Verisoft project. It was specified with PVS, implemented in Verilog, and runs on a Xilinx FPGA. A full stack from compiler to kernel to TCP/IP was built on it.

DLX (disambiguation)

DLX may refer to:

  • DLX, a RISC processor architecture
  • Dancing Links, a computer algorithm
  • Dlx (gene)
  • David Letterman Bypass, the proposed name of Interstate 465 in Indianapolis
  • 560 in Roman numerals

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